Format of PCI Configuration Data for Intel 82437VX:
Offset	Size	Description	)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 8086h, device ID 7030h)
		(revision ID 00h = A0 stepping)
 40h 15 BYTEs	reserved
 4Fh	BYTE	arbitration control (see #01109)
 50h	BYTE	PCI Control (see #01110)
 51h	BYTE	reserved
 52h	BYTE	cache control (see #01112)
 53h	BYTE	cache control extensions (see #01113)
 54h	WORD	SDRAM control (see #01114)
 55h	BYTE	reserved
 56h	BYTE	DRAM extended control (see #01115)
 57h	BYTE	DRAM control (see #01116)
 58h	BYTE	DRAM timing (see #01117)
 59h  7 BYTEs	Programmable Attribute Map registers 0-6 (see #01118)
 60h  5 BYTEs	DRAM Row Boundary registers 0-4
		each register N indicates amount of memory in rows 0-N in 4M
		  units (each row is 64 bits wide); the fifth row of memory (if
		  implemented) must contain either 8M or 16M, depending on
		  system configuration
		boundary register 4 (offset 64h) contains the total system
		  memory, which may not exceed 128M
 65h  2 BYTEs	reserved
 67h	BYTE	DRAM Row Type (high)
		defines memory type in DRAM row 4 in bits 4,0 (see #01119)
 68h	BYTE	DRAM Row Type (low) (see #01119)
 69h	BYTE	PCI TRDY timer (see #01122)
 6Ah  6 BYTEs	reserved
 70h	BYTE	Multi-Transaction Timer
		number of PCLKs guaranteed to the current agent before the
		  82437 will grant the bus to another PCI agent on request
 71h	BYTE	reserved
 72h	BYTE	System Management RAM control (see #01123)
 73h	BYTE	shared memory buffer control (see #01124)
 74h	BYTE	shared memory buffer start address, in 0.5MB units
		end address is top-of-memory at offset 64h or start of an
		  enabled PCI memory hole when top-of-memory is 16M
 76h  2 BYTEs	reserved
 78h	BYTE	graphics controller latency timers (see #01125)
 79h 135 BYTEs	reserved
SeeAlso: #00873,#01063,#01083,#01098,#01106