Format of PCI Configuration data for OPTi 82C861/82C871 PCI-to-USB Bus Bridge:
Offset	Size	Description	)
 00h 64	BYTEs	header (see #00878)
		(vendor ID 1045h, device ID C861h)
 40h  4 BYTEs	reserved for testing
 44h 10 BYTEs	reserved
 4Eh	BYTE	I2C control
		bits 7-5: reserved
		bit 4: I2C data output read-back (read-only)
		bit 3: I2C clock output read-back (read-only)
		bit 2: I2C data output
		bit 1: I2C clock output
		bit 0: I2C control enable
 4Fh	BYTE	reserved
 50h	BYTE	PCI host feature control
		bits 7-4: reserved
		bit 3: subsystem vendor ID register write disable
		bit 2: CLKRUN# enable
		bit 1: port 2 output disable
		bit 0: port 1 output disable
 51h	BYTE	interrupt assignment
		bit 7: host controller type 
		    0 = Viper-N+ (send 1 data phase on IRQ driveback)
		    1 = FireStar (send 2 data phases on IRQ driveback)
		bit 6: IRQ driveback enable
		bit 5: reserved
		bits 4-0: interrupt assignment
		    00000 = disabled
		    00001 = PCIRQ0# (default) to 00100 = PCIRQ3#,
		    00101 = ACPI0 to 01111 = ACPI10
		    10000 = IRQ0 to 11111 = IRQ15
 52h  2 BYTEs	reserved
 54h	DWORD	IRQ driveback address
		bits 1-0: reserved to 00 (read-only)
 58h 20 BYTEs	reserved
 6Ch	DWORD	reserved (test mode enable)
SeeAlso: #00878,#00929,#00939