Bitfields for Intel 82371MX Local Trap SMI Enable/Status registers:
Bit(s)	Description	)
 7-6	reserved
 5	IDE
 4	Audio
 3	COM
 2	DEV3
 1	DEV2
 0	DEV1
Note:	a set bit indicates in the Enable register turns generation of SMI# on
	  I/O accesses to the address region used by the selected device;
	  a set bit in the Status register indicates which trap caused an SMI#
	  interrupt.
SeeAlso: #01168,PORT xxxxh"Intel 82371"