`timescale 1ns / 1ps // Copyright (C) 2008 DJ Delorie // Distributed under the terms of the GNU General Public License, // either verion 2 or (at your choice) any later version. module top(ibin, nen, en, blank, lzblank, polarity, oseg2, oseg1, oseg0); input [7:0] ibin; input nen; input en; input blank; input lzblank; input polarity; output [6:0] oseg2; output [6:0] oseg1; output [6:0] oseg0; wire nen; wire en; wire blank; wire lzblank; wire polarity; reg [6:0] oseg2; reg [6:0] oseg1; reg [6:0] oseg0; wire [1:0] bcd2; wire [3:0] bcd1; wire [3:0] bcd0; reg [7:0] ibinh; reg blank2; reg blank1; reg blank0; reg lz2; reg lz1; wire [6:0] oseg2t; wire [6:0] oseg1t; wire [6:0] oseg0t; always @ (ibin, nen, en) begin if (en & ~ nen) ibinh = ibin; else ibinh = ibinh; end bcd b0 (ibinh, bcd2, bcd1, bcd0); always @ (bcd2, bcd1) begin lz2 = (bcd2 == 0) ? 1 : 0; lz1 = (bcd1 == 0) ? lz2 : 0; end always @ (lz2, lz1, lzblank, blank) begin blank2 = (lzblank & lz2) | blank; blank1 = (lzblank & lz1) | blank; blank0 = blank; end sevenseg012 s2 (bcd2, oseg2t); sevenseg s1 (bcd1, oseg1t); sevenseg s0 (bcd0, oseg0t); always @ (oseg2t, polarity, blank2) begin if (blank2) oseg2 = 7'bZ; else if (polarity) oseg2 = ~ oseg2t; else oseg2 = oseg2t; end always @ (oseg1t, polarity, blank1, blank2) begin if (blank1) oseg1 = 7'bZ; else if (polarity) oseg1 = ~ oseg1t; else oseg1 = oseg1t; end always @ (oseg0t, polarity, blank0) begin if (blank0) oseg0 = 7'bZ; else if (polarity) oseg0 = ~ oseg0t; else oseg0 = oseg0t; end endmodule